A Bias Tee for Broadband Measurement of Power Electronic Components

Editor's Note: The paper on which this article is based was originally presented at the 2021 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC, SI & PI), where it received recognition as the Best Symposium Paper. It is reprinted here with the gracious permission of the IEEE. Copyright 2022 IEEE.

In many EMC applications, passive components need to be characterized to provide simulation models and physical insight into the dominant processes within these components. Passive filters consist of inductors and capacitors, some of which are 3- or 4-terminal devices, such as common-mode chokes. For small signals, these components can be considered linear with respect to voltage and current. However, in many applications, non-linear effects must be considered and characterized. This can be achieved with a time-domain large-signal approach or by linearization around certain bias points. Linearized characterization of potentially non-linear devices such as filter inductors or capacitors requires simultaneous excitation of the small-signal evaluation signal and the large-signal bias, which is current for inductors and voltage for capacitors. The most commonly used method relies on a vector network analyzer (VNA) and a bias network to apply the large signal bias.

For higher current or voltage levels, external bias tees must be used for VNA measurements. In particular, when these span a wide frequency range, here from 9 kHz to 500 mHz, they present the following challenges:

This paper shows design details of a linear bias tee for a frequency range of 9 kHz – 500 mHz which can handle 10 A continuously, or 30 A for 10 minutes and can be biased up to 500 V. Although there are countless publications on bias tees for high frequency applications, there are relatively few in the low frequency range and even fewer suited for high DC currents and voltages. In [1] it is stated that "The proposed Bias-T was designed for the target values IDCmax = 1 A and UDCmax = 150 V at the lower frequency fmin = 2 mHz and at the current minimum bandwidth of Bmin of 100 mHz" while in [2] the targeted frequency range reaches from 300 kHz to 100 mHz with a maximum DC current of 3A. Both publications do not present any considerations regarding the protection concept and also target lower bandwidth and smaller DC currents and voltages. In [2], coils with iron core are used, which probably results in the need to make several calibrations for different DC current values to account for the influence of saturation effects. However, no information was given in this respect.

For very low frequencies there are also interesting active solutions for bias tees [3], which again cannot be used for higher frequencies. However, the bias tee published in this paper is intended to be used primarily for the measurement of conducted electromagnetic emissions, for which a lower frequency limit of 9 kHz is quite adequate. A passive solution is therefore preferred.

Although some of the concepts described regarding the construction of the individual components are already known in the literature, to the best of the authors’ knowledge, there are no publications yet on such a composition for the construction of a bias tee. The particular advantage of this special form of bias tee is the possible use for small-signal characterization of power electronic components while maintaining high large-signal bias currents and voltages. By measuring the S-parameters of various power electronic components and measuring the changes due to bias over a large frequency range, valuable data can be easily obtained for modeling the behavior of these components under large signal bias. Measurements of this configuration show good results regarding important properties of the tee, like insertion loss, return loss and temperature behavior.

Figure 1 shows four common bias tee consisting of a DC block capacitor and an RF decoupling inductor. The general topology of a bis tee is maintained in this design. The core challenge is the design of the components for the needed inductance, capacitance, voltage and current values and their physical arrangement in a bias tee such that four of those bias tees can be arranged to form a 4-port measurement system, like depicted. The schematic of the proposed bias tee is shown in Figure 2 and discussed in detail in the following sections.

Figure 1: Possible test setup for measuring a common mode choke

Figure 2: Schematic of the proposed bias tee

The capacitor in a bias tee acts as a DC block, allowing RF currents to pass in the frequency range of interest. Lower minimum frequencies require larger capacitance values to avoid influencing the RF path. If 2 Ω is set as upper impedance limit for the capacitor a value of 8.8 µF is needed at 9 kHz. Linearity requirements up to 500 V exclude the usage of high K ceramics or electrolytic capacitors. This constraint increases the size of the capacitors such that the upper frequency limit becomes a challenge. The parasitic inductances and parasitic capacitances of the capacitor arrangement needs to be utilized to obtain low RF losses in the RF path. This is realized by a distributed arrangement of the capacitors seen in Figure 3.

Figure 3: Design of the DC block capacitor with 50 Ω characteristic impedance. Copper layer thickness is not to scale. All dimensions are in mm.

To obtain a constant characteristic impedance of 50 Ω along the capacitor arrangement the structure must maintain a cross section that provides 50 Ω including the parasitic effects of the capacitors. To obtain the needed capacitance of about 8.8 µF a total of 13 capacitors of size 0.68 µF have been placed in parallel [4]. The capacitor has a width of 6 mm.

On a 1.6 mm FR-4 board a 3 mm wide trace leads to a 50 Ω characteristic impedance. To distribute the capacitances along the transmission line, thus to allow for a undisturbed TEM wave the capacitors are placed vertically, like it is shown in Figure 3. To match the trace width to the width of the capacitors two layers of 1.6 mm FR-4 are used creating a 6 mm wide microstrip line which allows placement of the capacitors without interrupting the RF path. Two carefully designed transitions guide the RF signal from the 3 mm wide trace to the 6 mm wide trace. Figure 4 shows the results of the designed microstrip line using a TDR measurement with a bandwidth of 14 GHz. It can be seen that the capacitive coupling of the TVS diodes used to protect the VNA, as discussed in the section "Protection Concept," have an influence on the line. This influence can be counteracted by changing the diameter of the microstrip line at the point where the diodes are connected.

Figure 4: TDR measurement of the designed capacitor with and without TVS diodes as protection device

Although the capacitors are voltage-dependent due to their dielectric (X7R), this only has a negative effect on the behavior of the bias tee in the lowest frequency range, where large capacitance plays a decisive role. Class 2 X7R capacitors promise a maximum capacitance change of 15 % at nominal voltage.

For the calculation of the necessary inductance values, a minimum impedance of 43 dBΩ (referred to 1 Ω) was aimed at. At the minimum frequency of 9 kHz this results in a necessary minimum inductance of about 2.5 mH. The needed bandwidth and current carrying capability poses several problems for the inductor design. High currents require thick wires which adds parasitics at high frequencies; not being able to use cores because of saturation effects increases the inductor size, which again is detrimental to the RF performance and the use of large value inductors increases the difficulty of over-voltage protection of the VNA in case the DUT current is suddenly interrupted. In addition, large coils have greater DC resistance and thus higher power dissipation, which leads to increased temperatures in the package (see the section "Temperature Behavior").

In order to optimize the behavior at high frequencies, a conical coil (L1), shown in Figure 5, was used. Following the design in [5] the conical inductor was connected to the 50 Ω microstrip line that holds the DC block. The advantages of a conical design over a cylindrical inductor can be seen in Figure 6. The conical shape improves the RF performance however, it offers less inductance compared to a cylindrical inductor having the same number of turns and length. Both inductors in the plot have the same inductance and do not use a magnetic core. Up to the resonance, no differences are visible. However, after the first resonance, the conical inductor shows a series of resonances maintaining in average higher impedance relative to its cylindrical partner. The distribution of these additional resonances depends on details of the winding, the wire diameter and the distance between the wires. The higher the frequency, the more important is the design of the tip of the conical inductor and its connection to the 50 Ω trace. According to [6] the inductance of the conical inductor can be derived from the inductances of related cylindrical and spiral inductors. The inductance of a spiral inductor in µH is given by Equation 1 where R is the mean radius of the inductor in mm, W is the radius difference on both cone ends in mm and N is the number of windings.

Figure 5: Design of the conical inductor with dimensions in millimeters

Figure 6: Comparison of the frequency characteristic of a conical and a helical inductor

(1)

The inductance of a cylindrical (helical) inductor is given by Equation 2, where H is the coil height in mm and again R and N are the mean radius and the number of windings respectively.

(2)

Using LS and LH the inductance of a conical inductor can be obtained by Equation 3 where α is the angle of the conical inductor, being 0° for a totally flat inductor.

(3)

For this coil an inductance of about 63 µH is calculated with the geometrical values given in Figure 5. For achieving an inductance value of 2.5 mH the conical inductor would need to be more than three times as long, which is why two further coils of higher inductance (L2 = 0.27 mH and L3 = 2.2 mH) had to be connected in series behind it to reach the desired inductance value. The coils have a total DC resistance of 300 mΩ and thus dissipate 30 W at 10 A DC current.

The coil assembly forms a complex system of the nominal coils and parasitic capacitances between the windings, to the enclosure and between the coils. This leads to a multitude of resonances, which was already shown in Figure 6 for the conical inductor itself. These resonances have a threefold negative effect on the system performance:

Thus, it is advisable to introduce losses that dampen the resonances. This will reduce the impedance at resonances and increase the impedance at anti-resonances. Of the several available damping methods, electrically lossy material placed near the conical inductor was used for the first stage inductor, represented by Rdamp in Figure 2. Magnetically lossy material would pose the risk of introducing non-linear behavior due to the large DC current. Placing a resistor across the conical inductor would add parasitic capacitance to the connection point at the DC block on the RF path. The disadvantage of the electrically lossy material is its blocking effect on the cooling of the coil.

For the other inductors adjustable resistors have been placed in parallel to allow for a smooth impedance behavior which leads to a smooth loss characteristic show in Figure 8.

A maximum permissible direct current of 10 A will store about 126.5 mJ of energy in the inductors. This energy is divided among the three inductors (EL1 = 3 mJ, EL2 = 13.5 mJ, EL3 = 110 mJ).

Without protection, a sudden interruption of current flow through the DUT, e.g., a solder joint breaks, will dissipate the stored energy into the VNA (RIP). Protective devices such as transient voltage suppressor (TVS) diodes are well suited to protect the VNA. If they are placed directly in the RF path, their capacitance needs to be kept small to avoid further disturbances on the RF path. However, those diodes cannot handle the energy. The problem is resolved by distributing diodes across the inductors. The high value inductors store most of the energy, but their electrical function is limited to lower frequencies, thus TVS having larger capacitance of about 100 pF can be used [7]. No TVS is placed across the conical inductor, instead 2.5 pF TVS are placed on the RF path [8].

A second protection problem arises from the 1.1 J stored in the DC block capacitors. If the DUT is suddenly shorted to GND the 8.8 µF charged at 500 V would be discharged into the VNA (RIP). The low capacitance diodes placed to protect against the energy in the conical inductor cannot handle the energy. A second level protection is needed. This is realized by placing polymer based snap back devices from the RF path to GND [9]. These devices offer very low capacitance < 0.05 pF, a fast turn on of 0.1 ns. After internal breakdown within the component, they clamp at about 25 V DC. The amount of energy in the DC block capacitor can destroy them and the TVS devices, but they protect the VNA in case of a short circuit.

An additional problem for this circuit is the internal DC block of the VNA. Since it has a small capacitance compared to the DC block of the bias tee, a capacitive voltage divider is created, which means that at high DC voltages, a voltage would always be present at the input of the VNA and could destroy it. Therefore, two parallel 10 kΩ resistors are connected between internal and external DC block against ground. These dissipate a slowly changing DC current until the large capacitor of the external DC block is full and the internal DC block can no longer be charged.

After initial measurements, discussed in the following section, an additional capacitor with 1.5 nF and resistor with 910 Ω was inserted between L1 and L2, as shown in Figure 2, to further flatten the insertion loss curve. Furthermore, an additional capacitor of 2200 µF was added to the DC port to ensure a well-defined impedance to ground which is independent of the impedance of the DC source. Figure 7 shows the complete bias tee with all components. These were installed in a die- cast aluminum housing, which on the one hand reduces the susceptibility to interference and on the other hand ensures temperature stability.

Figure 7: Picture of the bias tee in aluminum housing

The verification covers linear frequency response, temperature behavior and linearity check at high currents and voltages.

To verify the linear behavior the S-parameters of two identically built bias tees have been measured. Because of the well-defined impedance due to the large capacitor at the DC port, port 3 can be left open during calibration. In Figure 8 an insertion loss measurement of the two bias tees is depicted, which shows very satisfying results from 9 kHz up to a frequency of about 500 mHz with an insertion loss of less than 1 dB and an insertion flatness of about 0.5 dB. Above 500 mHz, the insertion loss increases to 2 dB at 1 GHz, largely due to the high frequency characteristics of the conical inductor. Measurements using conical coils with thinner wire showed better properties here but cannot pass the DC current. It can also be seen from the return loss measurement in Figure 9, that even though the two shown bias tees are built identically, their return loss differs quite significantly. This is the effect of slightly different coils and potentiometer settings. In general, one could create an S-parameter set for each bias tee and use this for de-embedding. Even though this procedure would result in better measurement performance, one would need the de-embedding profiles for each individual tee and must never interchange the bias tees for each measurement. Instead, a self-made calibration kit with previously measured de-embedding parameters was used. Two bias tees and the self-made calibration kit (TOSM) was used for calibration, which works regardless of the arrangement of the bias tees. For the final measurement, shown in Figure 1 a four-port calibration has to be done. In general, all calibration methods can run into the same limitations, which are small remaining non-linearities or mechanical changes due to heat or mechanical instability.

Figure 8: Insertion loss of two identically built bias tees

Figure 9: Return loss of two identically built bias tees

The DC resistance of the coils (RL1 = 0.1 Ω, RL2 = 0.04 Ω, RL3 = 0.16 Ω) leads to internal heating at high currents. A stress test of the bias tee was carried out in the course of an initial test. The bias tee was loaded with 10 A DC current for 30 minutes causing the temperature at the tip of the conical inductor to increase to 60 °C. No forced cooling was applied. No significant heating was detected elsewhere in the enclosure.

The maximum voltage at the input of the VNA in the event of a fault is specified by the manufacturer as 30 V. The protection circuit, described in Sec. II-D was tested by connecting two bias tees in series and a fuse with 10 A rated current which should simulate a sudden interrupt of current flow. A DC current of 25 A was applied to the test setup with a 50 Ω dummy load and a small capacitor as DC block instead of the VNA. The resulting voltage at the dummy VNA did not exceed the maximum allowed voltage of 30 V and the resulting energy of about 125 µJ does not pose any danger to the input of the VNA.

Figure 10 shows an S12 measurement of two bias tees connected in series at different DC bias currents. It can be seen that the DC bias current causes practically no difference in the behavior of the tees up to 25A.

Figure 10: Insertion loss of two bias tees in series

Figure 11 shows a test measurement of an inductor [10] at different DC bias currents between 0 A and 13 A. Saturation effects due to the DC bias current can be observed in the lower frequency range by a shift towards the right. At higher frequencies not much changes due to the bias current, since the permeability of the material has reduced to a level at which the flux cannot reach saturation levels.

Figure 11: Measurement of an inductor with different DC bias currents.

This paper shows a way to build a bias tee for power electronics applications. Especially if saturation effects of coils or larger filter elements in a low frequency range are to be investigated, this bias tee offers a possibility to tackle this problem with the help of vector network analysis. This allows to measure a device under test in magnitude and phase to gain detailed conclusions about its frequency behavior. The data can then be used to optimize filter circuits in real application situations, or to generate load-dependent models of these filters. The presented bias tee shows good frequency response over a wide frequency range and can be loaded with high DC currents and voltages. Measurements show that the behavior of the bias tee is not influenced by DC bias currents. When these bias currents are abruptly interrupted, the presented protection circuit serves to protect the measurement equipment.

The financial support by the Austrian Federal Ministry for Digital and Economic Affairs, the National Foundation for Research, Technology and Development, and the Christian Doppler Research Association is gratefully acknowledged.

bias teeChristoph MaierDavid PommerenkeemcieeeMichael Fuchsvector network analyzerVNA

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